Projects / Read and costed
AI in the chip itself
Horizon An idea with sources behind it and nothing built. Published so it can be argued with.
A robot that asks a data centre what to do has a network dependency in its reflexes. Putting the model in the silicon removes the round trip, and it is hard to do.
This area covers neuromorphic computing, the energy and memory walls that make it attractive, and what brain mapping has and has not contributed to it.
Drawn from Jo's survey, Parts III-A, III-B and IV.
The two walls
Conventional chips are limited by energy and by data movement: getting numbers to the arithmetic costs more than the arithmetic. Neuromorphic designs attack the second by keeping memory and compute together, which is also what a brain does.
What brain mapping has given chip design
On whether connectomics helps chip design, the survey concludes that a wiring diagram helps as a constraint and falls short of a blueprint. A map of the connections leaves open what the circuit computes.
What is not known here
The open items for this project. Work on it starts here.
- Whether any of this is reachable by a person outside a fab is unknown, and probably no.
- The specific chip-scale AI direction Jo pointed at needs its claims checked one by one before anything is written about it here.